What Happens When the Brush Is Bigger Than the Features You're Trying to Draw?
There’s a simple way to understand one of the biggest challenges in semiconductor manufacturing:
What happens when the brush is bigger than the features you're trying to draw?
That’s essentially the problem behind Intel’s struggles with advanced patterning—and why techniques like Directed Self-Assembly (DSA) were explored so aggressively around the 14nm era.
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The Limits of Traditional Lithography
Modern chips are built using photolithography—projecting patterns onto silicon using light.
But there’s a hard constraint:
You can’t reliably print features smaller than the wavelength (and process limits) of the light and optics you're using.
As features shrink:
edges blur lines merge or collapse variability explodes
At some point, your “brush” (the lithography system) is simply too large.
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Enter DSA: Let Chemistry Do the Work
Instead of forcing lithography to do everything, DSA takes a different approach:
1. Use lithography to define coarse guiding patterns 2. Let specially engineered polymers self-organize into finer structures
Think of it like:
sketching rough lines with a thick marker then letting the ink naturally split into finer, evenly spaced strands
DSA promised:
tighter pitches than lithography alone lower cost than extreme multi-patterning a bridge before EUV fully matured
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Why It Was So Appealing at 14nm
Around Intel’s 14nm generation, the industry hit a wall:
Multi-patterning complexity was exploding Yield sensitivity was rising Costs were scaling faster than performance gains
DSA looked like a way to:
sidestep physics constraints with materials science
Instead of fighting the brush size, you worked around it .
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Why It Didn’t Become the Main Path
DSA was elegant in theory—but brutal in practice.
Key issues:
Defect control : self-assembly isn’t perfectly deterministic Integration complexity : hard to fit into existing process flows Variability : small deviations → major electrical differences Tooling ecosystem : not mature enough at scale
In short:
letting materials “decide” structure introduced uncertainty chipmakers couldn’t tolerate
And in semiconductors, uncertainty kills yield .
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The Real Winner: EUV
While DSA tried to work around the brush problem, extreme ultraviolet (EUV) lithography attacked it directly:
shorter wavelength finer resolution fewer patterning steps
EUV didn’t eliminate all challenges—but it provided:
a more deterministic path forward
That mattered more than elegance.
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The Deeper Lesson
The DSA story isn’t just about one technique—it’s about how industries respond to hard limits.
You have two options:
1. Push the existing tool beyond its limits (multi-patterning) 2. Introduce a new paradigm (DSA, EUV)
DSA sat in the middle:
clever promising but ultimately too unpredictable
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Back to the Brush
When the brush is too big, you have three choices:
use multiple strokes (multi-patterning) change the brush (EUV) or let the paint organize itself (DSA)
Only one of those scaled cleanly.
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Why This Still Matters for Investors
These transitions aren’t just technical—they’re financial.
They determine:
who captures margin which suppliers win (lithography vs materials) where bottlenecks form
DSA didn’t win—but the problem it tried to solve is still shaping:
next-gen patterning materials innovation cost curves across the semiconductor stack
Market Implications: Who Wins When the Brush Changes?
The shift from DSA-like approaches to EUV wasn’t just technical—it reshaped the entire semiconductor supply chain.
Here’s how to think about it in terms of public companies:
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ASML — The New Bottleneck
If the problem is the brush being too large, ASML is the company that makes the smaller brush .
EUV adoption directly drives ASML revenue High barriers to entry (effectively a monopoly in EUV) Each new node increases dependence on their tools
Key insight:
The industry chose precision over clever workarounds —and that funnels value to ASML.
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Intel — Execution vs. Architecture
Intel explored alternatives like DSA more aggressively than peers.
Why that matters:
Indicates willingness to pursue non-consensus solutions But also reflects pressure when core execution lags
Intel’s current push:
Regain process leadership (Intel 18A and beyond) Heavy reliance on EUV and advanced patterning
Key question:
Are they back to leading the process curve—or still reacting to it?
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Taiwan Semiconductor Manufacturing Company — Pragmatic Dominance
TSMC largely avoided overcommitting to experimental approaches like DSA.
Instead, they:
scaled multi-patterning when needed adopted EUV when it was ready prioritized yield and predictability
Key insight:
In semis, the winner isn’t the most creative—it’s the most reliable at scale.
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Lam Research and Applied Materials — The Hidden Complexity Trade
Even though EUV simplified some steps, overall process complexity is still rising.
These companies benefit from:
deposition etching process control
Key dynamic:
Fewer lithography steps ≠ simpler manufacturing
Complexity just moves elsewhere—and these companies capture that value.
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What to Watch Next
The “brush vs. feature size” problem isn’t solved—it’s just moved forward.
Here are the next pressure points:
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1. High-NA EUV Adoption (ASML Dependency Increases)
Next-gen EUV tools promise:
even finer resolution fewer patterning steps
Watch for:
TSMC / Intel adoption timelines cost per wafer trends tool utilization rates
Signal:
If High-NA scales smoothly, ASML’s moat deepens further.
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2. Yield vs. Complexity Tradeoffs
As nodes shrink:
variability increases defect sensitivity rises
Watch:
yield disclosures (rare but revealing) delays in node transitions commentary from equipment suppliers
Signal:
If yields struggle, “clever” solutions (like DSA-like materials approaches) may re-emerge.
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3. Materials Innovation (A Quiet Comeback for DSA Concepts)
Even though classic DSA didn’t win, the idea behind it—using materials to assist patterning—hasn’t gone away.
Watch:
new resist technologies self-aligned patterning techniques hybrid approaches combining EUV + materials
Signal:
The industry may revisit “let the material help” — but in more controlled ways.
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4. Cost Per Transistor (The Real Scoreboard)
Ultimately, none of this matters if costs don’t improve.
Watch:
capex intensity (especially at Intel and TSMC) pricing power of foundries margin pressure across the stack
Signal:
If cost scaling breaks, the entire model shifts—not just the tools.
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Final Investor Takeaway
DSA failed not because it was wrong—but because:
Semiconductor manufacturing rewards control over elegance.
The market consistently favors:
deterministic processes scalable solutions predictable yields
That’s why:
ASML captured enormous value TSMC dominated execution Intel is still fighting to recover positioning
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Closing Thought
The “brush problem” never goes away—it just evolves.
And every time the industry hits that limit again, it creates:
a new bottleneck a new winner and a new opportunity for investors who understand where the constraint moves next
Final Thought
The history of semiconductors is full of ideas that were almost right .
DSA was one of them.
And those “almosts” are often where the most important signals are—if you know how to read them.